Cadence NC-Verilog Selected by Faraday Technology Corporation as Verilog Sign-off Simulator
SAN JOSE, Calif.--(BUSINESS WIRE)--Dec. 20, 2001--The Division of
Design Development in Faraday Technology Corporation, Taiwan, today
announced that it has selected the Cadence Design Systems
NC-Verilog® as its Verilog sign-off simulator. As a result,
NC-Verilog now provides Faraday designers with a more effective
solution to meet Verilog HDL needs for ASIC and SoC designs.
In qualifying NC-Verilog, Faraday applied various criteria
including sign-off scope of gate-level design styles, HDL language
support, single-cell verification, timing path checking, programming
language interface support, and event scheduling.
The Cadence® NC-Verilog simulator is the fastest, most memory
efficient, and most integrated Verilog simulator available. Unique
integrations include support for the Cadence wireless flow -- through
the Cadence Signal Processing Worksystem (SPW) connection -- and
complete mixed analog/digital support as part of Cadence AMS Designer.
Recent additions to NC-Verilog include very low-overhead integrated
code coverage and the Cadence Internet Learning Series (iLS) training.
Contact:
Cadence Design Systems, Inc.
Valerie J. Smith, 408/428-5795
vsmith@cadence.com
